1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of forming a metal wiring using a dual damascene process.
2. Description of the Related Art
With an increase in the integration of semiconductor devices, a multi-layered metal wiring structure is required, and the spacing between metal wirings has decreased. Thus, the parasitic resistance (R) effect and the parasitic capacitance (C) effects existing between adjacent conductors on a layer and between vertically adjacent wiring layers are potentially greater for highly-integrated semiconductor devices. Such parasitic resistance and capacitance degrade the electrical performance of the device due to a delay induced by RC. Also, the parasitic resistance and capacitance components increase the overall chip power dissipation and the amount of signal cross talk. Therefore, in ultra highly-integrated semiconductor devices, it is important to develop a technology of multi-layered wiring having a small RC.
In order to form a high performance multi-layered wiring structure having a low RC, a wiring layer must be formed of a metal having low resistivity and/or a dielectric layer having low permittivity must be used.
In order to lower the resistance in the metal wiring layer, research is actively being conducted into using a metal having low resistivity, e.g., copper, to form the metal wiring layer. But it is difficult to obtain a copper wiring by directly patterning a copper film using photolithography. Thus, a dual damascene process is usually used to form the copper wiring.
Also, in order to reduce the capacitance generated between the metal wiring layers, a technique of using a low dielectric film as an interlayer dielectric film between the metal wirings has been developed.
In the prior art, however, even if the low dielectric film is used as the interlayer dielectric film, a film formed of a material having relatively high permittivity such as a silicon nitride or a silicon oxynitride is used as a mask layer for patterning the interlayer dielectric film during the dual damascene process. As a result, the high permittivity mask layer remains between the interlayer dielectric film even after the device is completed, thus increasing the mean permittivity of the interlayer dielectric film. Consequently, the advantage of using the low dielectric film as the interlayer dielectric film is reduced.